Symmetric multiprocessing (SMP) is a variant of multiprocessing technology in which one instance of an operating system controls all processors, and in which memory is shared. ========================================================== Memroy是怎么share?shared-memory object 是不支持SMP的 SMP differs from asymmetric multiprocessing (AMP) in that an AMP system has a separate instance of an operating system executing on each processor (and each instance may or may not be the same type of operating system). ======================================================== 也就是说P4080的8个核上,AMP有些可以run Vxworks ,有些可以run其他的OS. VxWorks SMP is designed for symmetric target hardware. That is, each CPU has equivalent access to all memory and all devices. VxWorks SMP can therefore run on targets with multiple single-core processors or with multicore processors, as long as they provide a uniform memory access (UMA) architecture with hardware-managed cache-coherency. ============================================================= 啥是UMA archiecture ? SMP changes the conventional uniprocessor paradigm of priority-based preemptive multitasking programming, because it allows true concurrent execution of tasks and handling of interrupts. This is possible because multiple tasks can run on multiple CPUs, while being controlled by a single instance of an operating system. ======================================================= 真正的多任务 Because SMP systems allow for truly concurrent execution, the uniprocessor mechanisms for disabling (masking) interrupts and for suspending task preemption in order to protect critical regions are inappropriate for—and not available in—an SMP operating system. ======================================================= UP中的disable interrupt, suspend task等方法在SMP中不可以用了 SMP有另一套机制用于互斥. SMP特点: 1.Each CPU accesses the very same physical memory subsystem; there is no memory local to a CPU. 2. Each CPU has its own memory management unit that allows concurrent execution of tasks with different virtual memory contexts. 3. Each CPU has access to all devices. Interrupts from these devices can be routed to any one of the CPUs through an a programmable interrupt controller. This means that it is irrelevant which CPU executes interrupt service routines (ISRs) when handling interrupts. 4.Tasks and ISRs can be synchronized across CPUs and mutual exclusion enforced by using spinlocks. 5. Bus snooping logic ensures the data caches between CPUs are always coherent. This means that the operating system does not normally need to perform special data cache operations order to maintain coherent caches. However, this implies that only memory access attributes that allow bus snooping are used in the system. Restrictions in terms of memory access modes allowed in an SMP system, if any, are specific to a hardware architecture.

In an SMP configuration the entire physical memory space is shared between the CPUs. This memory space is used to store a single VxWorks SMP image (text, data, bss, heap). It is also used to store any real-time processes (RTPs) that are created during the lifetime of the system. Because both CPUs can potentially read from, write to and execute any memory location, any kernel task or user (RTP) task can be executed by either CPU.